Design one stage of a shift register (e.g., a D-type flip-flop) using basic gates. This does not have to have a ‘Preset’ function. Construct truth tables and/or excitation tables as appropriate and compare these with information in appropriate data sheets of TTL logic units.
The deliverable is a short document (1-2 pages) describing the design with appropriate diagrams. Sources of data or information should be acknowledged as references.
Design one each of a 4 stage asynchronous and synchronous counter using TTL logic units (e.g. appropriate D-type latches or JK-flips flops). Using data sheets for the device family you have chosen (e.g., LS – low power Schottky), estimate the propagation delay for the last bit in each case.
The deliverable is a short document (1-2 pages) describing the design with appropriate diagrams. Sources of data or information should be acknowledged as references.
Design a UART transmitter that meets the specifications of the original Assignments 2 and 3, and which includes the use of a shift register, a 4-bit synchronous counter and a clock. The design should involve stopping when the start bit, eight data bits and stop bit have been transmitted
Justify your design by detailing the functionality of the main sub-blocks of the design using tools such as truth tables, excitation tables and Karnaugh maps as appropriate. The technical analysis should cite relevant data from data sheets of the actual devices you would use to implement the design.
A careful description of the operation of the full design should be provided.
The deliverable is a formal report of around 3000-4000 words (up to 10 pages) including diagrams.
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