PSB5045EE Analog and Digital Electronics (ADE) PSB5045EE ADE ASSIGNMENT – QUESTION PAPER Answer: All 3 Questions.
Total 100 marks
Instructions: This is an individually assignment – you will be informed of your option by your lecturer. This main page must be included as the first page in your submission. Start each question on a new page and carefully identify your answers with the correct question number. Write your student ID and page number on every page of your answer. Upload your solutions in a single PDF file and all your simulation file into the PSB LMS system. Question 1 Design a 3-bit counter which counts in the following sequence:
001, 011, 010, 110, 111, 101, 001..
a. Sketch the stage diagram. (2 Marks)
b. Determine the number of states and tabulate the state table. (2 marks)
c. Tabulate state transition table (2 marks)
d. Tabulate state transition with excitation table using the flip flop assigned. (must include don’t care states) (10 marks)
e. Construct Karnaugh Map and get the simplified drive logic. (10 marks)
f. Implement the circuit and draw the relevant circuit diagram to match the sequence. (4 Marks)
g. Verify the performance of the circuit you designed by using the Multisim simulation software. Please paste both Multisim circuit you created and result with key timing diagrams obtain from the simulation into your report and upload these files and your assignment report into LMS. (10 marks)
(40 Marks)
Question 2 You are required to implement the Design of a 11011 Sequence Detector using Logic gates and flipflop and implement the circuit in Multisim Simulator.
a. Define overlap and non-overlap in sequence detector. (2 marks)
b. Tabulate the State Table and derive the State Diagram based on Overlap Mealy finite-state machine (FSM) model. (6 Marks)
c. Tabulate the State Transition Table with output. (2 Marks)
c. Determine the number of state variables needed and generate state the transistion table with output. (2 marks)
d. Tabulate the Output Table and use Karnaugh Map to derive the logic expression for output drive. (4 marks)
e. Design the drive logic using D flip flop, tabulate the Excitation Table and use Karnaugh Map to derive the logic expression for each drive.(6 marks)
f. Verify the performance of the circuit you have designed by using the Multisim simulation software. Please paste both Multisim circuit and result with key timing diagrams obtained from simulation into your report and upload all these files and your assignment report into LMS. (8 marks)
(30 Marks)
Question 3 Write VHDL codes to implement the below functionality:
a. Perform an Internet search and find the 74154 4-to-16 decoder datasheets. From the functional description given in the datasheet (15 Marks)
i. Write a VHDL description for a 74154 4-to-16 decoder. Use only STD_LOGIC and STD_LOGIC_VECTOR data types in constructing your design. (10 Marks)
ii. Simulate the code and verify the output waveform (5 Marks)
b. Implement the following truth table-based design in VHDL code. (15 Marks)
A B C D Y1 Y2 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 0 i. Write a VHDL code to implement the above truth Table (10 Marks)